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Session Track: General
Breakfast / Registration
  • Speaker:  
Time: Tuesday, April 10, 8:30am - 9:30am , Room: Upper Lobby
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Session Description: Breakfast / Registration

Session Track: Digital Implementation / Advanced Node
ADV101 (Arm) Case Study: Rapid Implementation of a 7nm Digital IP Test Chip
  • Speaker: Bob Eisenstadt, Staff Design Engineer, Arm 
Time: Tuesday, April 10, 9:30am - 10:10am , Room: Room 204
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Session Description: Each FinFET node and process has unique design rules and challenges for EDA tool usage, physical IP creation, implementation, and validation. Physical IP development has been driven by increasing features, performance, density, and power optimization. These drivers also increase the requirements and complexity of EDA tools and test chips. We present a test chip case study focusing on top-level implementation based on an engineering release of Arm® Artisan® libraries and Cadence® implementation tools targeting the 7nm FinFET process technology. The test chip contains Artisan GPIO’s, standard cell test blocks for standard cell libraries of 3 different heights, plus over 150+ memory instances from various Artisan memory compilers. To meet the expected design challenges of any new node, Arm has developed an automated design flow to support front-to-back test chip implementation and verification within a very tight design cycle. Arm Physical Design Group’s test-chip team leveraged the design flows from previous 7nm test chips to speed up the development of this test chip. Arm’s test-chip front-end design flow relies on automated generation of top level and block level netlists. The resulting RTL netlists are then synthesized using Cadence Genus™ Compiler. Arm’s front-end design flow is largely transparent across process nodes for RTL netlist generation and synthesis. The back-end design flow relied on Cadence® Innovus™. Arm’s back-end test chip design is performed in parallel with IP development. This provides a feedback loop to ARM’s IP developers that helps insure Arm’s physical IP is customer production ready. This case study will cover the following top-level design implementation topics. 1.) Test Chip overview, contents and hierarchy 2.) Innovus Setup 3.) Floor planning 4.) Mesh generation 5.) Placement 6.) Clock tree generation 7.) Routing

Bob Eisenstadt Bio: Bob Eisenstadt has been working on a wide range of IP test chips at ARM for the past 4+ years. Bob has 30 years of SOC design experience at a wide range of companies including: ARM, Pulsic, Rambus, Alchip, Qthink, Silicon Image, Silicon Graphics etc. Bob holds 6 US patents. Bob also has a BSEE from Cornell University plus MSEE and MBA degrees from Santa Clara University.
Session Track: Custom / Advanced Node
CUS101 (GLOBALFOUNDRIES) Automated Generation of PDK Library Documentation
  • Speaker: Romain Feuillette, Senior Member of Technical Staff - EDA/CAD Engineer - PDK & Libraries, GLOBALFOUNDRIES 
Time: Tuesday, April 10, 9:30am - 10:10am , Room: Room 210
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Session Description: The pressure of time to market can make it challenging for PDK teams to deliver not only high quality libraries, but also exhaustive Documentation. Yet, the role of a complete and well thought documentation is key. It allows the team to process an extra review of the consistency of the library and helps clarify the usage, hence anticipating most questions from our customers. Especially for advanced nodes, it is crucial for design teams to understand the complexity of the devices and their different options. There is different ways to tackle the challenge of documentation: One can write it all manually. It is very time consuming and not 100% reliable since it’s not automatically checked against the library itself. Also, every new release is a risk of creating a misalignment between the source (the library) and the documentation. Another way to approach this is full automation. This is reliable, but is missing some crucial information, like the detailed description of what parameter do in plain english for example. The approach we prefer to promote is an hybrid one: Generate about 80% of the document through a script pulling data from the library database. The remaining 20% is filled by PDK engineers (ex: descriptions of what pcells parameters do, etc..) The benefits from this approach are multiples: This is reliable and always aligned with the source library This provide by construction a checklist for the developers to filling the missing parameter descriptions, making the process of documenting easier and systematic. It generates and intermediate text report that can be easily used for analysing the difference between a PDK and its previous release. This is very useful for QA and also enables the automatic generation of the Release Notes. The Final documentation includes for each devices the symbol and layout view that have been extracted automatically from the OA database as well. Device specific chapters can even be saved as a documentation view within the library itself. In conclusion, we have today a generic tool that generates our documentation for several technologies. It is also optimizing our engineering resources. The highest benefit for us is to deliver to our customer a documentation that is reliable and consistent across the board.

Romain Feuillette Bio: MS in Electrical engineering/computer science, Romain Feuillette spent the first ten years of his career developing PCells and assuming several PDK leadership positions in Europe. He worked on a wide range of Analog/Mix signal technologies, including advanced-nodes and presented several times at CDNLIVE Silicon Valley. After moving to California in 2012, he was in charge of interfacing with EDA Vendors. He quickly expanded his role to also provide on site support to all US based customers, providing them CAD solutions tailored to their specific needs. Now tackling several exciting challenges with GLOBALFOUNDRIES he is a Senior Member of Technical Staff in their PDK organization.
Session Track: Front-End Design
FED101 (Broadcom) Rapid Turnaround EC with Conformal Smart LEC
  • Speaker: Nathan Hsiung, Master Engineer, Broadcom 
Time: Tuesday, April 10, 9:30am - 10:10am , Room: Room 203
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Session Description: Using latest and greatest SMART LEC technology to reduce overal LEC runtime , smart lec has powerful compare engine, along machine parallelism, which makes it compare faster. And for the cases of solve aborts, it solves it faster and can possibility solve abort that classic lec cannot solve. The other sweet part is that we don’t need to figure out which datapath option to set. In the past we had to run with experiments to find the right receipe for solving aborts.

Nathan Hsiung Bio: Nathan Hsiung is a Master Engineer in Broadcom Ltd Core Switching Group Division, responsible for Frontend Tool Methodology development and support. Nathan graduated with MSEE from Syracuse University, has 18 years of experience both in ASIC design and EDA Application, companies Nathan worked before including Xilinx, Synopsys, National Semiconductor and NEC Electronics. Nathan likes pingpong/running/travel in his spare time.
Session Track: IP / Block Verification
IPB101 (Cadence) The Cadence Verification Suite: Faster, Smarter Verification
  • Speaker: Frank Schirrmeister, Sr. Group Director, Product Management, Cadence Design Systems 
Time: Tuesday, April 10, 9:30am - 10:10am , Room: Room 206
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Session Description: As a combination of best in class engines for formal verification, simulation, emulation and FPGA based prototyping with a verification fabric offering verification management, debug, verification IP and portable stimulus for software driven SoC verification, the Cadence Verification Suite greatly accelerates time to market. This presentation will update on the latest improvements in the Verification Suite with a special focus on efficient integration of the engines, and will put the presentations in the two verification related CDNLive tracks in perspective. We will also provide and update on the latest trends driving the future of verification.

Frank Schirrmeister Bio: Frank Schirrmeister is senior group director for product management & marketing for emulation, FPGA based-prototyping and hardware/software enablement as part of the Cadence Verification Suite
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