Session Description: Each FinFET node and process has unique design rules and challenges for EDA tool usage, physical IP creation, implementation, and validation. Physical IP development has been driven by increasing features, performance, density, and power optimization. These drivers also increase the requirements and complexity of EDA tools and test chips. We present a test chip case study focusing on top-level implementation based on an engineering release of Arm® Artisan® libraries and Cadence® implementation tools targeting the 7nm FinFET process technology. The test chip contains Artisan GPIO’s, standard cell test blocks for standard cell libraries of 3 different heights, plus over 150+ memory instances from various Artisan memory compilers.
To meet the expected design challenges of any new node, Arm has developed an automated design flow to support front-to-back test chip implementation and verification within a very tight design cycle. Arm Physical Design Group’s test-chip team leveraged the design flows from previous 7nm test chips to speed up the development of this test chip.
Arm’s test-chip front-end design flow relies on automated generation of top level and block level netlists. The resulting RTL netlists are then synthesized using Cadence Genus™ Compiler. Arm’s front-end design flow is largely transparent across process nodes for RTL netlist generation and synthesis.
The back-end design flow relied on Cadence® Innovus™. Arm’s back-end test chip design is performed in parallel with IP development. This provides a feedback loop to ARM’s IP developers that helps insure Arm’s physical IP is customer production ready. This case study will cover the following top-level design implementation topics.
1.) Test Chip overview, contents and hierarchy
2.) Innovus Setup
3.) Floor planning
4.) Mesh generation
6.) Clock tree generation
Bob Eisenstadt Bio: Bob Eisenstadt has been working on a wide range of IP test chips at ARM for the past 4+ years. Bob has 30 years of SOC design experience at a wide range of companies including: ARM, Pulsic, Rambus, Alchip, Qthink, Silicon Image, Silicon Graphics etc. Bob holds 6 US patents. Bob also has a BSEE from Cornell University plus MSEE and MBA degrees from Santa Clara University.